1. Field of the Invention
The present invention relates to a MOS semiconductor device and a fabrication method of the same.
2. Description of the Background Art
A gate-controlled device in which main current is controlled by MOS structure gate is generally referred to as a MOS semiconductor device. Among those MOS-gate-controlled semiconductor devices known in the art are: a MOS-controlled thyristor (MCT) proposed by V. A. K. Temple, IEEE Trans. on Electron Devices, ED-33, page 1609; and an insulated gate transistor (IGT) suggested by B. J. Baliga, IEEE Electron Device Lett., EDL-14, page 452.
FIG. 28 shows a unit cell 100 of an IGT device as viewed from above and in cross section. In FIG. 28, an n type base layer 2 is disposed atop a p type emitter layer 1 so as to form a pn junction J.sub.1 at its interface with the p type emitter layer 1. Provided in the top central portion of the n type base layer 2 is a p type base layer 3 which consists of a relatively heavily doped p.sup.+ type region 3a and a p type region 3b. The p.sup.+ type region 3a is centered in the p type base layer 3 and surrounded by the p type region 3b. The n type base layer 2 and the p type base layer 3 abut at a pn junction J.sub.2 therebetween.
A ring shaped emitter layer 4 of n type material is selectively provided in an upper portion of the p type base layer 3. A portion of the top surface of the n type emitter layer 4 and an adjacent surface of the p.sup.+ type region 3a serve as a cathode surface 5. A pn junction J.sub.3 is formed at an interface between the p type base layer 3 and the n type emitter layer 4.
At its top surface, the p type region 3b includes a channel region CH. A gate oxide film 6 overlies the channel region CH and a region around the same. A gate electrode 7 is buried in the gate oxide film 6 and electrically connected to an external gate electrode G.
A cathode electrode 8 is disposed over the gate oxide film 6 as well as the cathode surface 5. This allows that the p type base layer 3 and the n type emitter layer 4 are in electrical contact with each other through the cathode electrode 8. However, the gate electrode 7 and the cathode electrode 8 are insulated from each other by the intervening gate oxide film 6. The cathode electrode 8 is electrically connected to an external cathode electrode K.
A bottom surface of the p type emitter layer 1 is an anode surface 9. An anode electrode 10 entirely covers the anode surface 9, thereby ensuring electrical contact between the p type emitter layer 1 and the anode electrode 10. The anode electrode 10 is connected to an external anode electrode A.
Behavior of the IGT unit cell 100 as above is as follows.
With a higher potential at the anode electrode 10 than the cathode electrode 8 while keeping the gate electrode 7 in a floating state, the pn junction J.sub.2 is reversely biased. Hence, no current flow would be generated between the anode electrode 10 and the cathode electrode 8.
An alternate case is where the anode electrode 10 is at a higher potential than the cathode electrode 8 and the gate electrode 7 is at a higher potential than the cathode electrode 8. With the p type region 3b being in electrical contact with the cathode electrode 8 via the p.sup.+ type region 3a while being coupled with the gate electrode 7 through the intervening gate oxide film 6, carrier charge storage occurs in the gate electrode 7 and the channel region CH and a channel is established in that region. The channel short circuits the n type base layer 2 to the n type emitter layer 4, initiating current flow between the anode electrode 10 and the cathode electrode 8. Thus, the unit cell 100 turns on.
If the gate voltage is removed in this on-state, the stored charge in the channel region CH is discharged, causing a exponential-like fall-off in a potential level around the channel region CH. As a result, the channel which has been short circuiting the n type base layer 2 and the n type emitter layer 4 disppears. Since the pn junction J.sub.2 is reverse biased, the disappearance of the channel blocks the current flow between the anode electrode 10 and the cathode electrode 8. This is the turn-off behavior of the unit cell 100.
An IGT pellet is constituted by connecting a plurality of (e.g., thousands of) the unit cells 100 parrallel in a matrix (FIG. 29). On the IGT pellet, the gate electrode 7, the cathode electrode 8 and the anode electrode 10 of one unit cell 100 are electrically connected to respective corresponding electrodes of an adjacent unit cell 100.
The gate electrodes 7 of the unit cells 100 are wire bonded with the external gate electrode G by aluminium or other wires (not shown). The anode electrodes 10 are brazed to the external anode electrode A.
Likewise, the cathode electrodes 8 are wipe bonded with the external cathode electrode K by aluminium or other wires.
The conventional MOS device requires that the cathode electrodes 8 and the external cathode electrode K are wire bonded to obtain electrical contact therebetween. However, as known in the art, a self-cooling capability of the cells is less excellent than where the electrical contact between the electrodes is ensured by pressure contact method (pressure contact structure).
FIG. 31 shows a portion, precisely around one unit cell 100, of the IGT pellet of FIG. 29 as adopting the pressure contact structure. In FIG. 31, a cathode electrode body 15 and the cathode electrode 8 are in pressure contact, thereby ensuring electrical conduction therebetween. In more details, the cathode electrode 8 consists of a recess portion 8a and a projecting portion 8b, the recess portion 8a being located directly on the cathode surface 5 and the projecting portion 8b being offset from the cathode surface 5 and overlying the gate oxide film 6. The cathode electrode body 15 is in pressure contact with the cathode electrode 8 only at the projecting portion 8b.
By pressure contacting the anode electrode 10 and an anode electrode body 17, electrical conduction therebetween is attained. This makes improvement possible in the self-cooling capability of the IGT pellet to dissipate heat developed in the same from the anode and the cathode electrodes 10 and 8.
Despite the enhanced the self-cooling capability, the conventional IGT has two problems.
The first problem stems from the direct pressure contact between the cathode electrode body 15 and the projecting portion 8b of the cathode electrode 8, this structure aiming at contacting the electrode bodies 15 and 17 and the electrodes 8 and 10, respectively. The gate oxide film 6 and the gate electrode 7 under the projecting portion 8b are films made of material such as silicon dioxide and polycrystalline silicon which are easily destroyed by mechanical stress. The state of the art MOS fabrication approach, however, still has a difficulty in controlling the gate oxide film 6 and the gate electrode 7 as to the uniformity in their thicknesses. Hence, when the cathode electrode body 15 and the electrode 8 are pressed against each other, the gate oxide film 6 and the gate electrode 7 are also subjected to the stress through the projecting portion 8b but only unevenly, and often deformed or destroyed. If this happens, the IGT pellet malfunctions.
The second problem relates to switching speed. To understand the second problem, the turn-on behavior of one IGT unit cell 100 will be described in detail. First, a control voltage V.sub.G is impressed on the external gate electrode G, causing charge storage in the gate electrode 7, and hence, increase in a potential V at the gate electrode 7. FIG. 30 is a graph plotting the increase in the potential V. The graph shows that with the control voltage V.sub.G impressed on the external gate electrode G at the time T.sub.0, the potential V at the gate electrode 7 rises exponentionally almost up to the control voltage V.sub.G. The upward curve of the voltage rise is expressed as: EQU V=V.sub.G .times.{1-exp (-t/.tau.)} (1)
where .tau. is time constant.
Now, assume that a threshold value of the potential V for creating the channel is V.sub.th, creation of the channel is completed in a time t.sub.0 after the control voltage V.sub.G was given to the external gate electrode G. In other words, the unit cell 100 turns on with time delay of t.sub.0 from the start of the gate voltage application. For high speed switching, the time duration t.sub.0 needs to be reduced. To reduce the time duration t.sub.0, the time constant .tau. must be small.
Since that the time constant .tau. is given as EQU .tau.=C.sub.iss .times.R.sub.g ( 2)
where C.sub.iss is an input capacitance and R.sub.g is a gate resistance of the unit cell 100, reduction in either the input capacitance C.sub.iss or the gate resistance R.sub.g lowers the time constant .tau.. The gate resistance R.sub.g herein defined is a resistance between the external gate electrode G and the gate electrode 7. The input capacitance C.sub.iss is a sum of a capacitance C.sub.1 between the gate electrode 7 and the cathode electrode 8, a capacitance C.sub.2 between the gate electrode 7 and the n type emitter layer 4, a capacitance C.sub.3 between the gate electrode 7 and the p type base layer 3 and a capacitance C.sub.4 between the gate electrode 7 and the n type base layer 2 (FIG. 32). In short, the input capacitance C.sub.iss is given as: EQU C.sub.iss =C.sub.1 +C.sub.2 +C.sub.3 +C.sub.4 ( 3)
The gate oxide film 6, which intervenes the gate electrode 7 and the cathode electrode 8, is usually formed by a silicon dioxide film to the thickness of about 1 .mu.m. Hence, the capacitance C.sub.1 per unit area is around 3.5 nF/cm.sup.2. Considering that the electrodes 7 and 8 share a large contacting area, the capacitance C.sub.1 accounts for a noneligible amount of the overall capacitance C.sub.iss. This large influence of the capacitance C.sub.1 may explain why success of the various past efforts to reduce the capacitances C.sub.2 and C.sub.4 is yet to be seen. Enough small time constant .tau., and hence, satisfactory improvement in switching speed have not been achieved.
Thus, the conventional IGTs are faced with these two problems. However, other MOS semiconductor devices are no exception in this regard.